vmul10uq

Vector Multiply-by-10 Unsigned Quadword

vmul10uq VRT,VRA

Multiplies the contents of a vector register by 10 and places the result in another vector register.

Details

The rightmost 128 bits of the product of src multiplied by the value 10 are placed into VSR[VRT+32]. Let src be the unsigned integer value in VSR[VRA+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src ←EXTZ(VSR[VRA+32])
prod ←(src << 3) + (src << 1)
VSR[VRT+32] ←CHOP128(prod)

Programming Note

This instruction multiplies the upper 64 bits of a vector register by 10 and stores the result in another vector register. Ensure that the Vector Facility is enabled (MSR.VEC=1); otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting and adding to achieve multiplication by 10, so be cautious with overflow if the input value is close to the maximum unsigned 64-bit integer.

Example

vmul10uq v1, v2

Encoding

Binary Layout
0
0
VRT
6
VRA
11
0
31
 
Format VX-form
Opcode 0x10000201
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register