xvcvsxdsp

VSX Vector Convert with round Signed Doubleword to Single-Precision format

xvcvsxdsp XT,XB

Converts signed doubleword elements of a vector register to single-precision floating-point and rounds the result.

Details

The instruction converts each signed doubleword element in VSR[XB] to an unbounded-precision floating-point value, rounds it to single-precision using the rounding mode specified by FPSCR.RN, and places the result into bits 0:31 and 32:63 of the corresponding doubleword element in VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 1
    reset_xflags()

    src ←bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)

    vresult.dword[i].word[0] ←bfp32_CONVERT_FROM_BFP(rnd)
    vresult.dword[i].word[1] ←bfp32_CONVERT_FROM_BFP(rnd)

    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support these instructions write the result into words 0 and 1 and words 2 and 3 of the result register, as is required by this version of the architecture.

Example

xvcvsxdsp vs1, vs3

Encoding

Binary Layout

Format XX2-form

Opcode 0xF00006E0

Extension VSX

Registers Altered FPSCR.FX, FPSCR.XX

Operands

XT
Target Vector Register
XB
Source Vector Register