vsraq

Vector Shift Right Algebraic Quadword

vsraq vD, vA, vB

Shifts the contents of a vector register right algebraically by a specified number of bits.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

773

21:31

Format VX-form

Opcode 0x10000305

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Shift Count Vector Register

Example

vsraq vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts the 128-bit contents of vector register vA right algebraically (with sign extension) by the number of bits specified in the low 7 bits of vB, placing the result in vD. Each of the two 64-bit doublewords in vA is independently shifted right with sign extension. No condition register or status field modifications occur.

Operation

shift_amount ← vB[57:63]
vD ← arithmetic_shift_right(vA, shift_amount)

Programming Note

The vsraq instruction is used for performing algebraic right shifts on quadword vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is derived from the low-order 7 bits of the second source register, and the result is stored in the destination register. Be cautious with alignment as it affects performance and correctness.