fdiv.

Floating Point Divide Record

fdiv. FC,FA,FB

Divides the contents of two floating-point registers and updates the condition register.

Encoding

Binary Layout

18

0:5

LI

6:29

AA

30

LK

31

 

Format XO-form

Opcode 0xFC000024

Extension Floating-Point

Operands

• FC
  Target Floating Point Register
• FA
  Source Floating Point Register
• FB
  Source Floating Point Register

Example

fdiv. fc, fa, fb

Registers Altered

CR0, FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For fdiv., the quotient of the contents of register FA and FB is placed into register FC.

Operation

if 'fdiv.' then
    FC <- (FA) / (FB)

Programming Note

The fdiv. instruction performs a floating-point division, storing the result in register FC. Ensure that registers FA and FB are properly initialized to avoid undefined behavior. This operation may raise exceptions if FB is zero or if there are overflow/underflow conditions; check FPSCR for exception flags after execution.