vminuh

Vector Minimum Unsigned Halfword

vminuh vD, vA, vB

Selects minimum value per halfword (unsigned).

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1090

21:31

 

Format VA-form

Opcode 0x10000242

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vminuh vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Selects the minimum unsigned value for each corresponding halfword pair from vA and vB, storing the results in vD. This is a vector operation that performs 8 independent halfword-wise minimum comparisons in parallel. No condition flags or status fields are affected.

Operation

for i in 0 to 7 do
  vD[16*i:16*i+15] ← MIN_UNSIGNED(vA[16*i:16*i+15], vB[16*i:16*i+15])
end for

Programming Note

The vminuh instruction is used to perform element-wise minimum operations on unsigned halfwords from two source vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data, but both source and destination vectors must be properly loaded into the vector registers VRA, VRB, and VRT respectively.