vminuh

Vector Minimum Unsigned Halfword

vminuh vD, vA, vB

Selects minimum value per halfword (unsigned).

Details

The vminuh instruction performs a vector minimum operation on unsigned halfwords. It compares each pair of corresponding halfwords from the source vectors VRA and VRB, selects the smaller value, and stores it in the destination vector VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]

   lt_flag ←EXTZ(src1) < EXTZ(src2)
   VSR[VRT+32].hword[i] ←lt_flag=1 ? src1 : src2
end

Programming Note

The vminuh instruction is used to perform element-wise minimum operations on unsigned halfwords from two source vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data, but both source and destination vectors must be properly loaded into the vector registers VRA, VRB, and VRT respectively.

Example

vminuh vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1090
21
 
Format VA-form
Opcode 0x10000442
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B