vmsumudm

Vector Multiply-Sum Unsigned Doubleword Modulo

vmsumudm VRT,VRA,VRB,VRC

Performs a horizontal add of the doubleword elements in VSR[VRA+32] using vmsumudm.

Details

The instruction performs a horizontal add of the doubleword elements in VSR[VRA+32]. It can also be used for horizontal subtract, multiply even unsigned doubleword, and multiply odd unsigned doubleword operations by setting specific values in VSR[VRB+32] and VSR[VRC+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
temp ←EXTZ(VSR[VRC+32])
do i = 0 to 1
    src1  ←EXTZ(VSR[VRA+32].dword[i])
    src2  ←EXTZ(VSR[VRB+32].dword[i])
    temp ←temp + (src1 × src2)
end
VSR[VRT+32] ←CHOP128(temp)

Programming Note

A horizontal add of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,1} and VSR[VRC+32] contains the quad-word integer value 0. A horizontal subtract of the doubleword elements in VSR[VRA+32] can be performed using vmsumudm when VSR[VRB+32] contains the doubleword integer values {1,-1} and VSR[VRC+32] contains the quad-word integer value 0. A multiply even unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 1 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0. A multiply odd unsigned doubleword operation can be performed using vmsumudm when the contents of doubleword element 0 of VSR[VRA+32] or VSR[VRB+32] are 0 and the contents of VSR[VRC+32] to 0.

Example

vmsumudm v1, v2, v3, v4

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
VRC
21
35
26
 
Format VA-form
Opcode 0x10000023
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VRC
    Source Vector Register
  • VA
    Source Vector Register
  • VB
    Source Vector Register
  • VC
    Source Vector Register