vprtybw

Vector Parity Byte Word

vprtybw vD, vB

Calculates the parity of each byte in a vector word and stores the result.

Encoding

Binary Layout

0:5

VRT

6:10

11:15

VRB

16:20

1538

21:31

Format VX-form

Opcode 0x10080602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VRB
Source Vector Register

Example

vprtybw vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vprtybw, the parity of each byte in the source vector register VRB is calculated and stored in the corresponding position in the target vector register VRT.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    s ←0
    do j = 0 to 3
        s ←s ⊕VSR[VRB+32].word[i].byte[j].bit[7]
    end
    VSR[VRT+32].word[i] ←CHOP32(EXTZ(s))
end

Programming Note

The vprtybw instruction calculates the parity of each byte in the source vector register and stores the result in the target vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words per iteration. Be cautious with alignment; both source and target registers must be properly aligned to avoid exceptions.