vslv

Vector Shift Left Variable

vslv VRT,VRA,VRB

Shifts the contents of vector elements left by a variable amount.

Encoding

Binary Layout

4

0:5

VRT

6:10

VRA

11:15

VRB

16:20

1860

21:31

 

Format VX-form

Opcode 0x10000744

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Shift Amount Vector Register

Example

vslv v1, v2, v3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts each element of the source vector left by a variable amount specified in the corresponding element of the shift amount vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.

Operation

for i in 0 to 15 do
  shamt ← (VRB[i*8:(i+1)*8-1]) & 0x7
  VRT[i*8:(i+1)*8-1] ← VRA[i*8:(i+1)*8-1] << shamt
end for

Programming Note

The vslv instruction is used to perform variable left shifts on each byte of a vector register. Ensure that the shift amounts in VSR[VRB+32] are within the valid range (0-7) to avoid unexpected results. This instruction operates at user privilege level and will raise an exception if the Vector Facility is not enabled.