vsrah

Vector Shift Right Algebraic Halfword

vsrah vD, vA, vB

Arithmetic right shift of halfwords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

836

21:31

Format VX-form

Opcode 0x10000344

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift

Example

vsrah vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts each of the 8 halfword elements in vA right arithmetically (with sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. The sign bit is replicated into vacated positions; bits shifted out are lost. No status flags are affected. This is a VMX/AltiVec instruction.

Operation

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← arithmetic_shift_right(vA[i*16:i*16+15], shift_amount)

Programming Note

The vsrah instruction is used to perform right algebraic shifts on halfword elements of a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The shift amount for each element is determined by the low-order 4 bits of the corresponding element in the second source vector. Be cautious with alignment as halfword operations require proper alignment to avoid undefined behavior.