vsrv

Vector Shift Right Variable

vsrv vTMP1, vSRC, vSHCT1

Shifts each element of the source vector right by a variable amount specified in another vector.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

1796

21:31

Format X-form

Opcode 0x10000704

Extension VMX (AltiVec)

Operands

vTMP1
Destination Vector Register
vSRC
Source Vector Register
vSHCT1
Shift Count Vector Register

Example

vsrv vtmp1, vsrc, vshct1

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts each element of the source vector right by a variable amount specified in the corresponding element of the shift count vector. The shift amount for each element is taken from the least significant bits of the corresponding element in VRB. No status flags are affected.

Operation

for i in 0 to 15 do
  shamt ← (VRB[i*8:(i+1)*8-1]) & 0x7
  VRT[i*8:(i+1)*8-1] ← VRA[i*8:(i+1)*8-1] >> shamt
end for

Programming Note

The vsrv instruction shifts each element of the source vector right by a variable amount specified in another vector. Ensure that the shift amounts are within the range of 0 to 127 to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions for normal operation.