vsubsws

Vector Subtract Signed Word Saturate

vsubsws vD, vA, vB

Subtracts 4 signed words with saturation.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1920

21:31

Format VX-form

Opcode 0x10000780

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vsubsws vd, va, vb

Registers Altered

MSR, VSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Subtracts each of 4 signed 32-bit elements in vB from the corresponding element in vA, with saturation to the signed 32-bit range [-2147483648, 2147483647]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed word value. No condition register fields are affected.

Operation

for i in 0 to 3 do
  result ← vA[32*i:32*i+31] - vB[32*i:32*i+31]
  if result < -2147483648 then vD[32*i:32*i+31] ← -2147483648
  elsif result > 2147483647 then vD[32*i:32*i+31] ← 2147483647
  else vD[32*i:32*i+31] ← result

Programming Note

The vsubsws instruction is useful for performing vectorized subtraction of signed words with saturation, ensuring that results do not overflow. Ensure that the VEC bit in the MSR register is set to enable vector operations; otherwise, a Vector_Unavailable exception will be raised. Be aware that the SAT flag in the VSCR register indicates if any result was saturated during the operation.