xsmaddasp

VSX Scalar Multiply-Add Type-A Single-Precision

xsmaddasp XT,XA,XB

Performs a single-precision floating-point multiply-add operation.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:31

Format XX3-form

Opcode 0xF0000008

Extension VSX

Operands

XT
Target Vector-Specific Register
XA
Source Vector-Specific Register
XB
Source Vector-Specific Register

Example

xsmaddasp vs1, vs2, vs3

Registers Altered

FPSCR, VSR[XT]

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xsmaddasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and then the result is added to the double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized and rounded to single-precision format.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[32×TX+T].dword[0] ←result64
  VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
  FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
  FPSCR.FR ←inc_flag
  FPSCR.FI ←xx_flag
else do
  FPSCR.FI ←0b0

Programming Note

See Table 7.10, “VSX Scalar Floating-Point Final Result,” on page 618.