xxsldwi

VSX Vector Shift Left Double by Word Immediate

xxsldwi XT,XA,XB,SHW

Shifts the contents of two vector registers left by a specified number of words and places the result into another vector register.

Encoding

Binary Layout
18
0:5
SH[5:0]
6:10
VRT[4:0]
11:15
VRA[4:0]
16:20
VRB[4:0]
21:31
 
Format XX3-form
Opcode 0xF0000010
Extension VSX

Operands

  • XT
    Target Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register
  • SHW
    Shift Amount in Words
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • SH
    Shift Amount (Immediate)

Example

xxsldwi vs1, vs2, vs3, 0

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts the concatenation of VSX vector registers XA and XB left by SHW words (0-3) and stores the result in XT. This instruction treats the two 128-bit source registers as a 256-bit value and extracts a 128-bit aligned window. No condition registers or status fields are affected.

Operation

shw ← SHW[1:0]
temp ← (XA || XB)  # concatenate as 256-bit value
XT ← temp[shw*32:(shw*32)+127]

Programming Note

The xxsldwi instruction is commonly used for shifting vector elements by a specified number of words. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. The shift amount must be within the range of 0 to 3, as it specifies the word position to align the result. This instruction operates at the user privilege level and does not generate exceptions for valid shifts; however, misalignment or exceeding the shift limit can lead to undefined behavior.