xxlandc

VSX Vector Logical AND with Complement

xxlandc XT, XA, XB

vD = vA & ~vB

Details

The xxlandc instruction performs a logical AND operation between the contents of VSR[XA] and the bitwise complement of the contents of VSR[XB]. The result is then placed into VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
VSR[32×TX+T] ← VSR[32×AX+A] & ¬VSR[32×BX+B]

Programming Note

The xxlandc instruction is used for performing a bitwise logical AND operation between the contents of two vector registers, where one register's bits are complemented before the operation. Ensure that the VSX (Vector Scalar Extensions) facility is enabled in the MSR (Machine State Register) to avoid an exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.

Example

xxlandc vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
444
21
 
Format XX3-form
Opcode 0xF00001BC
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B