xxlandc

VSX Vector Logical AND with Complement

xxlandc XT, XA, XB

vD = vA & ~vB

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

444

21:31

 

Format XX3-form

Opcode 0xF0000450

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xxlandc vs1, vs2, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bitwise logical AND operation between XT and the bitwise complement of XB, storing the result in XT. The operation is XT ← XT & ~XB on all 128 bits. No condition register or status field modifications occur.

Operation

XT ← XA & ~XB

Programming Note

The xxlandc instruction is used for performing a bitwise logical AND operation between the contents of two vector registers, where one register's bits are complemented before the operation. Ensure that the VSX (Vector Scalar Extensions) facility is enabled in the MSR (Machine State Register) to avoid an exception. This instruction operates on 128-bit vectors and requires proper alignment of the input and output registers.