mulhhwu

Multiply High Halfword Unsigned

mulhhwu RT, RA, RB

Unsigned Multiply High Halfword.

Encoding

Binary Layout

4

0:5

RT

6:10

RA

11:15

RB

16:20

8

21:30

0

31

 

Format XO-form

Opcode 0x10000010

Extension Embedded

Operands

• RT
  Target
• RA
  Src A
• RB
  Src B

Example

mulhhwu r3, r4, r5

Related

More in Embedded

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the zero-extended top halfword of RA by the zero-extended top halfword of RB, storing the low 32 bits of the product in RT. This is an unsigned 16×16→32 multiply operation on the upper halves. No condition register or status flags are affected.

Operation

a ← (RA[0:15])
b ← (RB[0:15])
RT ← (a × b)[32:63]