mtsr

Move To Segment Register

mtsr SR, RS

Legacy 32-bit segment register write.

Encoding

Binary Layout

31

0:5

RS

6:10

SR

11:15

/

16:20

210

21:30

/

31

 

Format X-form

Opcode 0x7C0001A4

Extension Base

Operands

• SR
  Segment Reg
• RS
  Source

Example

mtsr 0, r3

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Move the contents of GPR RS into the specified 32-bit segment register SR. This is a legacy instruction used in 32-bit PowerPC address translation and is not available in 64-bit mode. No status fields are affected.

Operation

SR ← RS[32:63]