mtvsrbmi

Move to Vector Scalar Register with Bit Mask Immediate

mtvsrbmi VRT,bm

Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.

Encoding

Binary Layout

0:5

VRT

6:10

11:15

16:25

26:30

Format XO-form

Opcode 0x10000014

Extension Base

Operands

VRT
Target vector scalar register that receives the byte mask pattern generated from the immediate value.
IMM8
8-bit immediate value where each bit controls the corresponding byte element (1 = 0xFF, 0 = 0x00).

Example

mtvsrbmi vs1, 0, 0xFF

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves an 8-bit immediate value into a VSR (Vector Scalar Register) with each bit of the immediate controlling whether the corresponding byte element is set to all-ones (0xFF) or all-zeros (0x00). This is a Base category instruction that does not affect condition register or other status fields. The instruction provides a quick way to create byte-level masks in vector registers.

Operation

for i in 0 to 7 do
  if IMM[i] = 1 then
    VSR_target[i*8:(i+1)*8] ← 0xFF
  else
    VSR_target[i*8:(i+1)*8] ← 0x00
end for

Programming Note

The mtvsrbmi instruction is useful for initializing vector registers with specific byte patterns based on an immediate bit mask. Ensure that the immediate value correctly reflects the desired byte-wise initialization to avoid unexpected results. This instruction operates at user privilege level and does not raise exceptions under normal conditions.