mtsrin

Move To Segment Register Indirect

mtsrin RS, RB

Indirect write of segment register using RB.

Encoding

Binary Layout

31

0:5

RS

6:10

/

11:15

RB

16:20

242

21:30

/

31

 

Format X-form

Opcode 0x7C0001E4

Extension Base

Operands

• RS
  Source
• RB
  Effective Addr

Example

mtsrin r3, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Move the contents of GPR RS into the segment register selected by bits 0-3 of GPR RB. This is an indirect write of the 32-bit segment register and is not available in 64-bit mode. No status fields are affected.

Operation

SR_index ← RB[0:3]
SR[SR_index] ← RS[32:63]