mulhdu

Multiply High Doubleword Unsigned

mulhdu RT, RA, RB

Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

9

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000012

Extension Base

Operands

• RT
  Target
• RA
  Src A
• RB
  Src B

Example

mulhdu r3, r4, r5

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two 64-bit unsigned integers (RA and RB) and stores the upper 64 bits of the 128-bit unsigned result in RT. The overflow flag is not set as the full 128-bit product is well-defined for unsigned multiplication. If Rc=1, CR0 is updated based on the result.

Operation

prod ← (RA) *u (RB); RT ← prod[64:127]; if Rc then CR0 ← (RT < 0, RT > 0, RT = 0, SO)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.