mtspr

Move To Special Purpose Register

mtspr SPR, RS

Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).

Encoding

Binary Layout

0:5

6:10

SPR

11:20

467

21:30

Format XFX-form

Opcode 0x7C0003A6

Extension Base

Operands

SPR
Special Purpose Register ID (Reordered bits)
RS
Source Register

Example

mtspr 9, r3

// Move r3 to Count Register (CTR).

Registers Altered

AMR, IAMR, UAMOR, BESCR, BESCRU, HMER, TBL, TBU, SPR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves the contents of a general-purpose register to a special-purpose register (such as CTR, LR, XER, FPSCR, or others). The SPR field is reordered from its 10-bit encoding in the instruction. Privilege level and results depend on which SPR is targeted; some SPRs are supervisor-only. No condition register flags are set by this instruction itself.

Operation

SPR_index ← (SPR[5:0] || SPR[10:5])
SPR[SPR_index] ← RS

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
mtxer
mtlr
mtctr
mtppr
mtppr32

Programming Note

spr0=1 if and only if writing the register is privileged. Execution of this instruction specifying an SPR number with spr0=1 when the privilege state of the thread does not permit the access causes one of the following: MSRPR=1: Privileged Instruction type Program interrupt, MSRHV PR=0b00 or MSRS HV PR=0b010 and the SPR is always an ultravisor resource (independent of the contents of SMFCTRL): Privileged Instruction type Program interrupt, LPCREVIRT=0: Privileged Instruction type Program interrupt, LPCREVIRT=1: Hypervisor Emulation Assistance interrupt, MSRS HV PR=0b010 and the SPR is PTCR, DAWRn, DAWRXn, or CIABR when they are ultravisor privileged for the operation: Hypervisor Emulation Assistance interrupt.