mtspr

Move To Special Purpose Register

mtspr SPR, RS

Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).

Details

The mtspr instruction moves the contents of a general-purpose register RS to a special-purpose register specified by SPR. If the designated special-purpose register is 32 bits long, only the low-order 32 bits of register RS are placed into the designated special-purpose register.

Pseudocode Operation

switch (n)
    case (13):
        if MSRHV PR = 0b10 then
            SPR(13) ← (RS)
        else if MSRHV PR = 0b00 then
            SPR(13) ← ((RS) & AMOR) | ((SPR(13)) & ¬AMOR)
        else
            SPR(13) ← ((RS) & UAMOR) | ((SPR(13)) & ¬UAMOR)
    case (29,61):
        if MSRHV PR = 0b10 then
            SPR(n) ← (RS)
        else
            SPR(n) ← ((RS) & AMOR) | ((SPR(n)) & ¬AMOR)
    case (157):
        if MSRHV PR = 0b10 then
            SPR(157) ← (RS)
        else
            SPR(157) ← (RS) & AMOR
    case (336):
        SPR(336) ← (SPR(336)) & (RS)
    case (800):
        BESCR ← BESCR | (RS)
    case (801):
        BESCRU ← BESCRU | (RS)32:63
    case (802):
        BESCR ← BESCR & ¬(RS)
    case (803):
        BESCRU ← BESCRU | ¬((RS)32:63)
    case (158, 808, 809, 810, 811):
        default:
            if length(SPR(n)) = 64 then
                SPR(n) ← (RS)
            else
                SPR(n) ← (RS)32:63

Programming Note

spr0=1 if and only if writing the register is privileged. Execution of this instruction specifying an SPR number with spr0=1 when the privilege state of the thread does not permit the access causes one of the following: MSRPR=1: Privileged Instruction type Program interrupt, MSRHV PR=0b00 or MSRS HV PR=0b010 and the SPR is always an ultravisor resource (independent of the contents of SMFCTRL): Privileged Instruction type Program interrupt, LPCREVIRT=0: Privileged Instruction type Program interrupt, LPCREVIRT=1: Hypervisor Emulation Assistance interrupt, MSRS HV PR=0b010 and the SPR is PTCR, DAWRn, DAWRXn, or CIABR when they are ultravisor privileged for the operation: Hypervisor Emulation Assistance interrupt.

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
mtxer
mtlr
mtctr
mtppr
mtppr32

Example

mtspr 9, r3

Encoding

Binary Layout

SPR

467

Format XFX-form

Opcode 0x7C0003A6

Extension Base

Registers Altered AMR, IAMR, UAMOR, BESCR, BESCRU, HMER, TBL, TBU, SPR

Operands

SPR
Special Purpose Register ID (Reordered bits)
RS
Source Register