sraw

Shift Right Algebraic Word

sraw RA, RS, RB

Performs an arithmetic right shift (sign bit replicated) on a 32-bit word. Updates Carry (CA) if bits are shifted out.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

792

21:30

Rc

31

 

Format X-form

Opcode 0x7C000630

Extension Base

Operands

• RA
  Target Register
• RS
  Source Register
• RB
  Shift Amount Register

Example

sraw r3, r4, r5

// r3 = r4 >> r5 (Signed 32-bit).

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Arithmetically shift the 32-bit word in RS right by the number of bits specified in RB[27:31], replicating the sign bit into vacated positions. The result is placed in RA. The CA bit in XER is set if any 1-bits are shifted out from a negative value, otherwise cleared. If Rc=1, CR0 is updated based on the result.

Operation

n ← RB[27:31]
if n = 0 then
  RA ← RS
  CA ← 0
else if n < 32 then
  shifted ← RS >> n
  if RS[0] = 1 ∧ (RS & ((1 << n) - 1)) ≠ 0 then
    CA ← 1
  else
    CA ← 0
  RA ← shifted
else
  if RS[0] = 1 then
    RA ← -1
    CA ← 1
  else
    RA ← 0
    CA ← 0
if Rc = 1 then
  CR0 ← (RA = 0) || LT || GT || SO

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.