sync

Synchronize

sync
sync L
hwsync
lwsync
ptesync
plwsync
stncisync
stcisync
stsncisync
stcisync

Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.

Details

The sync instruction is execution synchronizing. However, address translation and reference and change recording associated with subsequent instructions may be performed before the sync instruction completes. The memory barrier provides additional ordering function such that if a given instruction that is the result of a store in set B is executed, all applicable storage accesses in set A have been performed with respect to the processor executing the instruction to the extent required by the associated memory coherence properties.

Pseudocode Operation

if SC != 0 then
    switch(SC)
        case(1): stncisync
        case(2): stcisync
        case(3): stsync
    else switch(L)
        case(0): hwsync
        case(1): lwsync
        case(2): ptesync
        case(4): phwsync
        case(5): plwsync

Programming Note

sync serves as both a basic and an extended mnemonic. The Assembler will recognize a sync mnemonic with two operands as the basic form, and a sync mnemonic with one operand or with no operand as an extended form.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
hwsync
lwsync
ptesync
plwsync
stncisync
stcisync
stsncisync

Example

sync 0

Encoding

Binary Layout
31
0
/
6
/
8
L
31
598
/
 
Format X-form
Opcode 0x7C0004AC
Extension Base

Operands

  • L
    Level (0=Heavy, 1=Light)
  • SC
    Store Caching Inhibited Sync Control