sync
Synchronize
sync L,SC
Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.
Encoding
Binary Layout
31
0:5
/
6:10
/
11:15
L
16:20
598
21:30
/
31
Operands
-
L
Level (0=Heavy, 1=Light) -
SC
Store Caching Inhibited Sync Control
Example
sync 0
// Full hardware fence.
Related
Across architectures
Memory Barrier / Fence : how x86, ARM, RISC-V, and PowerISA each do this.
More in Base
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Synchronizes memory operations by ensuring all instructions preceding the sync complete before the sync completes, and no subsequent instructions are initiated until after sync completes. The L field specifies the synchronization scope: L=0 (hwsync) enforces a heavy-weight synchronization across all storage types, while L=1 (lwsync) provides a lighter-weight barrier suitable for most memory ordering. The SC field (bits 9-10) controls store-caching-inhibited synchronization for specific storage classes. No condition or status registers are affected.
Operation
Synchronize memory operations as specified by L and SC fields; ensure prior instructions complete before this instruction completes; ensure subsequent instructions do not begin until this instruction completes.Extended Mnemonics
| Extended Mnemonic | Equivalent Instruction |
|---|---|
| hwsync | sync L=0,SC=0 |
| lwsync | sync L=1,SC=0 |
| ptesync | sync L=2,SC=0 |
| phwsync | sync L=4,SC=0 |
| plwsync | sync L=5,SC=0 |
| stncisync | sync SC=1 |
| stcisync | sync SC=2 |
| stsync | sync SC=3 |
Programming Note
sync serves as both a basic and an extended mnemonic. The Assembler will recognize a sync mnemonic with two operands as the basic form, and a sync mnemonic with one operand or with no operand as an extended form.