sync

Synchronize

sync
sync L
hwsync
lwsync
ptesync
plwsync
stncisync
stcisync
stsncisync
stcisync

Ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and no subsequent instructions are initiated until after the sync instruction completes.

Details

Synchronizes memory operations by ensuring all instructions preceding the sync complete before the sync completes, and no subsequent instructions are initiated until after sync completes. The L field specifies the synchronization scope: L=0 (hwsync) enforces a heavy-weight synchronization across all storage types, while L=1 (lwsync) provides a lighter-weight barrier suitable for most memory ordering. The SC field (bits 9–10) controls store-caching-inhibited synchronization for specific storage classes. No condition or status registers are affected.

Pseudocode Operation

Synchronize memory operations as specified by L and SC fields; ensure prior instructions complete before this instruction completes; ensure subsequent instructions do not begin until this instruction completes.

Programming Note

sync serves as both a basic and an extended mnemonic. The Assembler will recognize a sync mnemonic with two operands as the basic form, and a sync mnemonic with one operand or with no operand as an extended form.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
hwsync
lwsync
ptesync
plwsync
stncisync
stcisync
stsncisync

Example

sync 0

// Full hardware fence.

Encoding

Binary Layout
31
0
/
6
/
8
L
31
598
/
 
Format X-form
Opcode 0x7C0004AC
Extension Base

Operands

  • L
    Level (0=Heavy, 1=Light)
  • SC
    Store Caching Inhibited Sync Control