stwcx.

Store Word Conditional Indexed

stwcx. RS, RA, RB

Stores a word from a register to memory if the reservation is valid and matches the address used in the corresponding lwarx instruction.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

150

21:30

1

31

 

Format X-form

Opcode 0x7C00012D

Extension Base

Operands

• RS
  Source
• RA
  Base
• RB
  Index

Example

stwcx. r3, r4, r5

Registers Altered

CR0, XER

Related

Across architectures

Atomic Compare and Swap : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The stwcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) formed by adding the contents of registers RA and RB, provided that a reservation exists for this EA and the reservation length is 4 bytes. If the reservation does not exist or the conditions are not met, no store is performed.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 4 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 4) ← (RS)32:63
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 4) ← (RS)32:63
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0

Programming Note

Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.