sthcx.

Store Halfword Conditional Indexed

sthcx. RS, RA, RB

Stores a halfword from a register to memory conditionally based on a reservation.

Encoding

Binary Layout

011111

0:5

6:10

11:15

16:20

10110

21:30

101101

Format X-form

Opcode 0x7C0005AD

Extension Base

Operands

RS
Source
RA
Base
RB
Index

Example

sthcx. r3, r4, r5

Registers Altered

CR0, XER

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The sthcx. instruction stores the upper half of the contents of register RS into memory at the effective address (EA) if a reservation exists and meets certain conditions. The EA is calculated as the sum of RA and RB, with RA being zero-extended to 64 bits. If the reservation length is not 2 bytes or the real storage location does not match the reservation, the store may be undefined or no store may occur.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
if RESERVE then
    if RESERVE_LENGTH = 2 &
       RESERVE_ADDR = real_addr(EA) then
        MEM(EA, 2) ← (RS)48:63
        undefined_case ← 0
        store_performed ← 1
    else
        z ← smallest real page size supported by implementation
        if RESERVE_ADDR ÷ z = real_addr(EA) ÷ z then
          undefined_case ← 1
        else
          undefined_case ← 0
          store_performed ← 0
else
    undefined_case ← 0
    store_performed ← 0
if undefined_case then
    u1 ← undefined 1-bit value
    if u1 then
      MEM(EA, 2) ← (RS)48:63
    u2 ← undefined 1-bit value
    CR0 ← 0b00 || u2 || XERSO
else
    CR0 ← 0b00 || store_performed || XERSO
RESERVE ← 0

Programming Note

Succeeds only if a valid reservation exists on the target address. Sets CR0[EQ] to 1 on success, 0 on failure. Must always be used in a retry loop that re-executes the load-reserve instruction on failure.