vcmpsq

Vector Compare Signed Quadword

vcmpsq BF,VRA,VRB

Compares the signed integer values in two vector registers and updates the condition register.

Encoding

Binary Layout

0:5

6:8

VRA

9:10

VRB

11:31

Format VX-form

Opcode 0x10000141

Extension VMX (AltiVec)

Operands

BF
Condition Register Field
VRA
Vector Register A
VRB
Vector Register B
VRT
Target Vector Register

Example

vcmpsq cr0, v2, v3

Registers Altered

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpsq, the signed integer value in VSR[VRA+32] is compared with the signed integer value in VSR[VRB+32]. The comparison flags are placed into CR field BF.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTS(VSR[VRA+32])
src2 ←EXTS(VSR[VRB+32])
lt_flag ←src1 < src2
gt_flag ←src1 > src2
eq_flag ←src1 = src2
CR.field[BF] ←lt_flag<<3 | gt_flag<<2 | eq_flag<<1

Programming Note

The vcmpsq instruction compares two signed quadword values from vector registers and sets the condition register (CR) field BF based on the comparison results. Ensure that the Vector Facility is enabled by checking and setting MSR.VEC before using this instruction. Be cautious of potential exceptions if the Vector Facility is not available.