vavguh

Vector Average Unsigned Halfword

vavguh vD, vA, vB

Computes (a+b+1)/2 for halfwords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1090

21:31

Format VA-form

Opcode 0x10000442

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vavguh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the average of corresponding unsigned halfwords in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 8 independent halfword elements in parallel. No condition flags or status fields are affected.

Operation

for i in 0 to 7 do
  vD[16*i:16*i+15] ← ((vA[16*i:16*i+15] + vB[16*i:16*i+15] + 1) >> 1)[15:0]
end for

Programming Note

The vavguh instruction is used to compute the average of corresponding halfwords from two source vectors, rounding up. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-bit unsigned integers and stores the result in the destination vector. Be cautious of overflow when adding the two source halfwords before rounding.