vcmpeqfp

Vector Compare Equal Floating-Point

vcmpeqfp VRT,VRA,VRB

Compares the elements of two vector registers for equality and stores the result in a third vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x100000C6

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpeqfp v1, v2, v3

Registers Altered

CR0, XER

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpeqfp, each element of VSR[VRA+32] is compared to the corresponding element of VSR[VRB+32]. If they are equal, the corresponding element of VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_EQ_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.