vcmpequw

Vector Compare Equal Word

vcmpequw VRT,VRA,VRB
vcmpequw. VRT,VRA,VRB

Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s.

Details

For vcmpequw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If they are equal, the corresponding word in VSR[VRT+32] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
do i = 0 to 3
   src1 ←VSR[VRA+32].word[i]
   src2 ←VSR[VRB+32].word[i]
   if src1 = src2 then do
      VSR[VRT+32].word[i] ←0xFFFF_FFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].word[i] ←0x0000_0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

vcmpequw v1, v2, v3

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
Rc
21
 
Format VC-form
Opcode 0x10000086
Extension VMX (AltiVec)
Registers Altered CR6

Operands

  • vD
    Target (Mask)
  • vA
    Source A
  • vB
    Source B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register