vsldbi
Vector Shift Left Double by Bit Immediate
vsldbi VRT,VRA,VRB,SH
Shifts the contents of two vector registers left by a specified number of bits and places the result into another vector register.
Encoding
Binary Layout
0
VRT
VRA
VRB
0
SH
22
Operands
-
VRT
Target Vector Register -
VRA
Source Vector Register -
VRB
Source Vector Register -
SH
Shift Amount (0-7)
Example
vsldbi v1, v2, v3, 3
Related
More in VMX (AltiVec)
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
The contents of VSR[VRA+32] concatenated with the contents of VSR[VRB+32] are shifted left by SH bits. The result is placed into VSR[VRT+32].
Operation
if MSR.VEC=0 then
Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32] ← vsrc.bit[SH:SH+127]Programming Note
This instruction is used to perform a left shift on the concatenated contents of two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount (SH) must be within the range of 0 to 127 bits. Be cautious with alignment as the operation involves concatenating and shifting double quadword values.