ldci

Load Doubleword Caching Inhibited

ldci RT, RA, RB

Loads a doubleword bypassing the cache.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

887

21:30

/

31

 

Format X-form

Opcode 0x7C0006EB

Extension Base

Operands

• RT
  Target
• RA
  Base
• RB
  Index

Example

ldci r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a doubleword (64 bits) from memory at address (RA + RB) with caching inhibited, storing the result in RT. This instruction bypasses the cache hierarchy and is used for memory-mapped I/O operations in 64-bit mode. No condition registers are affected.

Operation

EA ← (RA) + (RB); RT ← [EA]