ldci

Load Doubleword Caching Inhibited

ldci RT, RA, RB

Loads a doubleword bypassing the cache.

Details

Loads a doubleword (64 bits) from memory at address (RA + RB) with caching inhibited, storing the result in RT. This instruction bypasses the cache hierarchy and is used for memory-mapped I/O operations in 64-bit mode. No condition registers are affected.

Pseudocode Operation

EA ← (RA) + (RB); RT ← [EA]

Example

ldci r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
887
21
/
31
 
Format X-form
Opcode 0x7C0006EB
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index