xsmaxcdp

VSX Scalar Maximum Type-C Double-Precision

xsmaxcdp XT, XA, XB

Computes the maximum of two double-precision floating-point values and stores the result in a vector scalar register.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

152

21:31

 

Format XX3-form

Opcode 0xF0000400

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xsmaxcdp vs1, vs2, vs3

Registers Altered

FPSCR (FX, VXSNAN)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the maximum of two double-precision floating-point scalar values and stores the result in the target VSR. The operation follows the IEEE 754 maximum semantics where positive zero is greater than negative zero, and any comparison with NaN returns NaN. This instruction is part of the VSX category and does not set CR or XER flags.

Operation

XT_dp ← maxc_dp(XA_dp, XB_dp)

Programming Note

xsmaxcdp can be used to implement the C/C++/Java conditional operation (x>y)?x:y for single-precision and double-precision arguments. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.