xscvsdqp

VSX Scalar Convert Signed Doubleword to Quad-Precision

xscvsdqp vD, vB

Converts a signed doubleword integer from VSR[VRB+32] to quad-precision floating-point in VSR[VRT+32].

Encoding

Binary Layout

63

0:5

vD

6:10

/

11:15

vB

16:20

756

21:30

/

31

 

Format X-form

Opcode 0xFC0A0688

Extension VSX

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector-Scalar Register
• VRB
  Source Vector-Scalar Register

Example

xscvsdqp vd, vb

Registers Altered

FPSCR (FPRF, FR, FI)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts the signed integer value in doubleword element 0 of VSR[VRB+32] to quad-precision floating-point format and stores it in VSR[VRT+32]. The FPSCR.FPRF, FPSCR.FR, and FPSCR.FI fields are updated accordingly.

Operation

if MSR.VSX=0 then VSX_Unavailable()
src ← bfp_CONVERT_FROM_SI64(VSR[VRB+32].dword[0])
result ← bfp128_CONVERT_FROM_BFP(src)
VSR[VRT+32] ← result
FPSCR.FPRF ← fprf_CLASS_BFP128(result)
FPSCR.FR ← 0
FPSCR.FI ← 0

Programming Note

This instruction is commonly used for converting signed integers to quad-precision floating-point numbers in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. The conversion respects standard rounding rules, and the FPSCR flags are updated accordingly. Be cautious of potential overflow or underflow conditions when dealing with very large or small integers.