xsdivqp

VSX Scalar Divide Quad-Precision

xsdivqp vD, vA, vB

Divides the contents of two quad-precision floating-point registers and places the result in another register.

Details

Divides the quad-precision floating-point operand in VSR vA by the quad-precision operand in VSR vB, placing the quotient in VSR vD, with IEEE 754 rounding and exception handling. This VSX instruction updates FPSCR flags including division-by-zero, invalid operation, and underflow/overflow conditions.

Pseudocode Operation

vD ← vA ÷ vB
FPSCR ← updated with exception flags (ZX, XX, UX, OX, VXSNAN, VXIDI, VXDZ, etc.)

Programming Note

The xsdivqp instruction is used for dividing two quad-precision floating-point numbers. Be cautious of division by zero, which results in infinity or quiet NaN, and set appropriate flags. Handle infinities and zeros carefully as they can lead to special cases like zero or infinity in the result. Ensure that operands are correctly aligned and consider performance implications when using this instruction in loops.

Example

xsdivqp vd, va, vb

Encoding

Binary Layout
63
0
FRT
6
FRA
11
FRB
16
546
21
Rc
31
 
Format X-form
Opcode 0xFC000448
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector-Specific Register
  • VRA
    Source Vector-Specific Register
  • VRB
    Source Vector-Specific Register