xsdivqp

VSX Scalar Divide Quad-Precision

xsdivqp vD, vA, vB

Divides the contents of two quad-precision floating-point registers and places the result in another register.

Details

The xsdivqp instruction divides the contents of VSR[VRA+32] by the contents of VSR[VRB+32] and stores the result in VSR[VRT+32]. The operation follows specific rules for handling special cases like NaNs, infinities, and zeros.

Pseudocode Operation

if src2 == 0 then
    if src1 == 0 then
        tgt <- quiet(src2)
        vxzdz_flag <- 1
    else if src1 > 0 then
        tgt <- +Infinity
        vxidi_flag <- 1
    else
        tgt <- -Infinity
        vxidi_flag <- 1
else if src2 == +Infinity then
    if src1 == 0 then
        tgt <- quiet(src2)
        vxzdz_flag <- 1
    else if src1 > 0 then
        tgt <- +Zero
    else
        tgt <- -Zero
else if src2 == -Infinity then
    if src1 == 0 then
        tgt <- quiet(src2)
        vxzdz_flag <- 1
    else if src1 > 0 then
        tgt <- -Zero
    else
        tgt <- +Zero
else if src1 is NaN or src2 is NaN then
    tgt <- dQNaN
    vxsnan_flag <- 1
else
    tgt <- Div(src1, src2)
if tgt == +Infinity or tgt == -Infinity then
    zx_flag <- 1

Programming Note

The xsdivqp instruction is used for dividing two quad-precision floating-point numbers. Be cautious of division by zero, which results in infinity or quiet NaN, and set appropriate flags. Handle infinities and zeros carefully as they can lead to special cases like zero or infinity in the result. Ensure that operands are correctly aligned and consider performance implications when using this instruction in loops.

Example

xsdivqp vd, va, vb

Encoding

Binary Layout
63
0
FRT
6
FRA
11
FRB
16
546
21
Rc
31
 
Format X-form
Opcode 0xFC000444
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector-Specific Register
  • VRA
    Source Vector-Specific Register
  • VRB
    Source Vector-Specific Register