vminsd

Vector Minimum Signed Doubleword

vminsd VRT,VRA,VRB

Compares the signed doublewords of two vector registers and stores the minimum values in a third vector register.

Details

For vminsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] is compared. The smaller value is stored in the corresponding position in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ← VSR[VRA+32].dword[i]
    src2 ← VSR[VRB+32].dword[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].dword[i] ← lt_flag=1 ? src1 : src2
end

Programming Note

This instruction is used to perform element-wise minimum comparison on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the operands, so negative numbers are correctly handled. There are no specific alignment requirements for the data in the vector registers.

Example

vminsd v1, v2, v3

Encoding

Binary Layout
0
4
VRT
16
VRA
21
VRB
26
 
Format VX-form
Opcode 0x100003C2
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register