xstdivdp

VSX Scalar Test for software Divide Double-Precision

xstdivdp BF,XA,XB

Performs a double-precision floating-point division and sets condition flags based on the result.

Details

The xstdivdp instruction performs a double-precision floating-point division of src1 by src2. It also sets condition flags based on various error conditions or special cases.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
src1 ← VSR[32×AX+A].dword[0]
src2 ← VSR[32×BX+B].dword[0]
e_a ← src1.bit[1:11] - 1023
e_b ← src2.bit[1:11] - 1023
fe_flag ← IsNaN(src1) | IsInf(src1) | IsNaN(src2) | IsInf(src2) | IsZero(src2) | (e_b <= -1022) | (!IsZero(src1) & ((e_a - e_b) >= 1023)) | (!IsZero(src1) & ((e_a - e_b) <= -1021))
fg_flag ← IsInf(src1) | IsInf(src2) | IsZero(src2) | IsDen(src2)
fl_flag ← xsredp_error() <= 2^-14
CR[BF] ← 0b1 || fg_flag || fe_flag || 0b0

Programming Note

The xstdivdp instruction is used for performing double-precision floating-point division and setting condition flags based on various error conditions or special cases. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of division by zero, overflow, underflow, and NaN/Infinity values, as these can set specific condition flags in the CR register.

Example

xstdivdp cr0, vs2, vs3

Encoding

Binary Layout
18
0
BF
6
XA
9
XB
11
 
Format XX3-form
Opcode 0xF00001E8
Extension VSX
Registers Altered CR (field BF)

Operands

  • BF
    Condition Register Field
  • XA
    Index for Source Vector Register (src1)
  • XB
    Index for Source Vector Register (src2)