xstdivdp

VSX Scalar Test for software Divide Double-Precision

xstdivdp BF,XA,XB

Performs a double-precision floating-point division and sets condition flags based on the result.

Encoding

Binary Layout

18

0:5

BF

6:8

XA

9:10

XB

11:31

 

Format XX3-form

Opcode 0xF00001E8

Extension VSX

Operands

• BF
  Condition Register Field
• XA
  Index for Source Vector Register (src1)
• XB
  Index for Source Vector Register (src2)

Example

xstdivdp cr0, vs2, vs3

Registers Altered

CR (field BF)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Tests for special cases in double-precision floating-point division (such as division by zero or invalid operands) and sets a condition register field with the result. No actual division is performed; instead, the instruction is used to check operand validity before software performs the division. This instruction requires VSX support.

Operation

BF ← test_division(XA[0:63], XB[0:63])
CR[BF:BF+3] ← BF

Programming Note

The xstdivdp instruction is used for performing double-precision floating-point division and setting condition flags based on various error conditions or special cases. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of division by zero, overflow, underflow, and NaN/Infinity values, as these can set specific condition flags in the CR register.