vncipherlast

Vector Inverse Cipher Last

vncipherlast vD, vA, vB

Performs the final round of AES decryption.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1353

21:31

 

Format VX-form

Opcode 0x10000549

Extension Vector Crypto

Operands

• vD
  Target
• vA
  State
• vB
  Round Key

Example

vncipherlast vd, va, vb

Registers Altered

MSR

Related

More in Vector Crypto

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs the final round of AES decryption on a 128-bit block, applying the inverse MixColumns and InvSubBytes operations followed by AddRoundKey with the provided round key. This instruction is part of the Vector Crypto extension and operates on 128-bit values held in vector registers. No status flags are affected.

Operation

vD ← InvCipherLast(vA, vB)

Programming Note

The vncipherlast instruction is used to complete the AES inverse cipher process by applying the final transformations. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input State and RoundKey must be correctly loaded into VSR registers VRA+32 and VRB+32, respectively, to avoid incorrect results.