xvf32ger

VSX Vector Float32 GER (Rank-1 Update)

xvf32ger AT, XA, XB

Performs a vector floating-point general element-wise reduction with rank-1 update.

Details

Performs a rank-1 outer product of two FP32 (single-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. This reduction-style MMA operation multiplies corresponding FP32 elements and accumulates the products with appropriate rounding and exception behavior. No condition registers or status fields are modified.

Pseudocode Operation

for i = 0 to 15 do
  for j = 0 to 15 do
    prod ← (fp32)XA[32×i:32×i+31] × (fp32)XB[32×j:32×j+31]
    ACC[AT][result_lane] ← ACC[AT][result_lane] + prod
  end for
end for

Programming Note

The xvf32ger instruction is commonly used for matrix operations, specifically rank-1 updates. Ensure that the input matrices in VSR[XA] and VSR[XB] are correctly aligned and formatted as 4x2 matrices to avoid incorrect results. This operation requires floating-point precision and may raise exceptions if inputs are out of range or if there are NaNs or infinities involved.

Example

xvf32ger acc0, vs2, vs3

Encoding

Binary Layout
0
0
6
6
9
9
11
11
16
16
21
21
27
27
AXBX
31
 
Format XX3-form
Opcode 0xF000001B
Extension MMA
Registers Altered ACC

Operands

  • AT
    Accumulator
  • XA
    Src A (FP32)
  • XB
    Src B (FP32)