fctidu

Floating Convert with round Double-Precision To Unsigned Doubleword format

fctidu FRT,FRB

Converts a double-precision floating-point value to an unsigned 64-bit integer using rounding.

Encoding

Binary Layout

0:5

FRT

6:10

11:15

FRB

16:20

942

21:30

Format X-form

Opcode 0xFC00075C

Extension Floating-Point

Operands

FRT
Target Floating Point Register
FRB
Source Floating Point Register

Example

fctidu f1, f3

Registers Altered

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x0000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 264-1, then the result is 0xFFFF_FFFF_FFFF_FFFF, and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, then the result is 0x0000_0000_0000_0000, and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit unsigned-integer format, and XX is set to 1 if the result is inexact.

Operation

if src is a NaN then
    FRT <- 0x0000_0000_0000_0000
    VXCVI <- 1
    if src is an SNaN then VXSNAN <- 1
else
    rounded_value <- round(src, RN)
    if rounded_value > 264-1 then
        FRT <- 0xFFFF_FFFF_FFFF_FFFF
        VXCVI <- 1
    else if rounded_value < 0 then
        FRT <- 0x0000_0000_0000_0000
        VXCVI <- 1
    else
        FRT <- convert_to_unsigned_integer(rounded_value)
        XX <- is_inexact(FRT)
if not enabled Invalid Operation Exception then
    place result into FRT

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.