vrfiz

Vector Round to Floating-Point Integer towards Zero

vrfiz vD, vB

Rounds 4 floats to integer (trunc).

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

586

21:31

 

Format VX-form

Opcode 0x1000024A

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vrfiz vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rounds each of four 32-bit floating-point elements in vB towards zero (truncate) and stores the integer results as floating-point values in vD. This instruction operates on the VMX/AltiVec extension and does not modify condition registers or exception flags.

Operation

for i in 0 to 3:
  vD[32*i:32*i+31] ← RoundTowardZero(vB[32*i:32*i+31])

Programming Note

The vrfiz instruction rounds each single-precision floating-point value in the source vector towards zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment of the data for optimal performance.