vpextd

Vector Parallel Bits Extract Doubleword

vpextd vD, vA, vB

Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1421

21:31

Format VX-form

Opcode 0x1000058D

Extension VMX (AltiVec)

Operands

vD
Target
vA
Source
vB
Mask
VRT
Target Vector Register
VRA
Source Vector Register A
VRB
Source Vector Register B

Example

vpextd vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Extracts bits from vA based on bit-position indices specified in vB, placing extracted bits into the corresponding doubleword elements of vD. The instruction operates on 64-bit doubleword elements, where vB contains bit indices (0-63) that select which bits from vA are gathered into vD. This is a VMX extension instruction with no condition register or status flag updates.

Operation

for i in 0 to 1 do
  vD[i*64:(i+1)*64] ← 0
  for j in 0 to 63 do
    if vB[i*64+j] < 64 then
      vD[i*64+j] ← vA[i*64 + vB[i*64+j:i*64+j+5]]
    else
      vD[i*64+j] ← 0

Programming Note

The vpextd instruction is used to extract bits from one vector register based on the bit positions specified in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on each doubleword element of the vectors, so ensure proper alignment and indexing to avoid unexpected results.