vpextd

Vector Parallel Bits Extract Doubleword

vpextd vD, vA, vB

Extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register.

Details

The vpextd instruction extracts bits from one vector register based on the bit positions specified in another vector register and places them into a third vector register. The operation is performed on each doubleword element of the vectors.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    result ←0
    m ←0
    k ←0
    do while(m < 64)
        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
            result.bit[63-k] ←
               VSR[VRA+32].dword[i].bit[63-m]
            k ←k + 1
        end
        m ←m + 1
    end
    VSR[VRT+32].dword[i] ←result
end

Programming Note

The vpextd instruction is used to extract bits from one vector register based on the bit positions specified in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on each doubleword element of the vectors, so ensure proper alignment and indexing to avoid unexpected results.

Example

vpextd vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1421
 
Format VX-form
Opcode 0x1000058D
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Source
  • vB
    Mask
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register A
  • VRB
    Source Vector Register B