machhwsu

Multiply Accumulate High Halfword Signed Unsigned

machhwsu RT, RA, RB

Mixed Sign Multiply Accumulate High Halfword with Saturation.

Details

Multiplies the high halfword (bits 0–15) of RA (signed) by the high halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.

Pseudocode Operation

product ← EXTS(RA[0:15]) × EXTZ(RB[0:15])
result ← RT + product
if result > 2147483647 then
  RT ← 2147483647
  SPEFSCR[SAT] ← 1
elif result < -2147483648 then
  RT ← -2147483648
  SPEFSCR[SAT] ← 1
else
  RT ← result

Example

machhwsu r3, r4, r5

Encoding

Binary Layout
4
0
RT
6
RA
11
RB
16
76
21
0
31
 
Format XO-form
Opcode 0x10000098
Extension Embedded

Operands

  • RT
    Acc/Dest
  • RA
    Src A
  • RB
    Src B