machhwsu
Multiply Accumulate High Halfword Signed Unsigned
machhwsu RT, RA, RB
Mixed Sign Multiply Accumulate High Halfword with Saturation.
Encoding
Binary Layout
4
0:5
RT
6:10
RA
11:15
RB
16:20
76
21:30
0
31
Operands
-
RT
Acc/Dest -
RA
Src A -
RB
Src B
Example
machhwsu r3, r4, r5
Related
More in Embedded
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Multiplies the high halfword (bits 0-15) of RA (signed) by the high halfword of RB (unsigned), adds the 32-bit product to RT, and saturates the result to the signed 32-bit range if overflow occurs. This is part of the Embedded (SPE) category and sets the SAT bit in SPEFSCR if saturation occurs.
Operation
product ← EXTS(RA[0:15]) × EXTZ(RB[0:15])
result ← RT + product
if result > 2147483647 then
RT ← 2147483647
SPEFSCR[SAT] ← 1
elif result < -2147483648 then
RT ← -2147483648
SPEFSCR[SAT] ← 1
else
RT ← result