vabsduw

Vector Absolute Difference Unsigned Word

vabsduw vD, vA, vB

Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register.

Details

For vabsduw, the absolute difference of each word element from VSR[VRA+32] and VSR[VRB+32] is calculated and stored in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])

    if src1 > src2 then
        VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)
    else
        VSR[VRT+32].word[i] ←CHOP32(src2 + ¬src1 + 1)
end

Programming Note

This instruction calculates the absolute difference of each word element between two vector registers and stores the result in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The operation handles unsigned integers, so be cautious with negative values if they are interpreted as signed. This instruction does not require any specific alignment for the data it operates on.

Example

vabsduw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1155
 
Format VA-form
Opcode 0x10000483
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register