lvsl

Load Vector for Shift Left Indexed

lvsl VRT,RA,RB

Loads a vector pattern suitable for shifting left indexed.

Details

The lvsl instruction loads the left shift control value for unaligned vector operations into a VSX register. This control value can be used by subsequent vperm instructions to align data correctly.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
sh ←(((RA=0) ? 0 : GPR[RA]) + GPR[RB]).bit[60:63]
switch(sh)
    case(0x0): v←0x000102030405060708090A0B0C0D0E0F
    case(0x1): v←0x0102030405060708090A0B0C0D0E0F10
    case(0x2): v←0x02030405060708090A0B0C0D0E0F1011
    case(0x3): v←0x030405060708090A0B0C0D0E0F101112
    case(0x4): v←0x0405060708090A0B0C0D0E0F10111213
    case(0x5): v←0x05060708090A0B0C0D0E0F1011121314
    case(0x6): v←0x060708090A0B0C0D0E0F101112131415
    case(0x7): v←0x0708090A0B0C0D0E0F10111213141516
    case(0x8): v←0x08090A0B0C0D0E0F1011121314151617
    case(0x9): v←0x090A0B0C0D0E0F101112131415161718
    case(0xA): v←0x0A0B0C0D0E0F10111213141516171819
    case(0xB): v←0x0B0C0D0E0F101112131415161718191A
    case(0xC): v←0x0C0D0E0F101112131415161718191A1B
    case(0xD): v←0x0D0E0F101112131415161718191A1B1C
    case(0xE): v←0x0E0F101112131415161718191A1B1C1D
    case(0xF): v←0x0F101112131415161718191A1B1C1D1E
VSR[VRT+32] ←v

Programming Note

The lvsl instruction can be used to create a permute control vector for vperm instructions. It is useful for loading and storing unaligned data, as well as rotating or shifting the contents of a VSR.

Example

lvsl v1, r4, r5

Encoding

Binary Layout
31
0
VRT
6
RA
11
RB
16
6
21
/
31
 
Format X-form
Opcode 0x7C00000C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • RA
    Source General Purpose Register
  • RB
    Source General Purpose Register