lvsl

Load Vector for Shift Left Indexed

lvsl VRT,RA,RB

Loads a vector pattern suitable for shifting left indexed.

Encoding

Binary Layout

31

0:5

VRT

6:10

RA

11:15

RB

16:20

6

21:30

/

31

 

Format X-form

Opcode 0x7C00000C

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

lvsl v1, r4, r5

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Creates a shift-left permutation pattern based on the effective address (RA+RB) modulo 16 and loads it into VRT. This instruction is part of the VMX (AltiVec) category and is typically used to set up permutation vectors for unaligned vector loads. It does not update condition registers.

Operation

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
shift_amount ← EA[28:31]
VRT ← PermutationPattern(shift_amount, "shift_left")

Programming Note

The lvsl instruction can be used to create a permute control vector for vperm instructions. It is useful for loading and storing unaligned data, as well as rotating or shifting the contents of a VSR.