vmaddfp

Vector Multiply-Add Floating-Point

vmaddfp VRT,VRA,VRB,VRC

Performs a multiply-add operation on vector elements.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

VRC

21:31

Format VA-form

Opcode 0x1000002E

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Source Vector Register

Example

vmaddfp v1, v2, v3, v4

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmaddfp, the instruction multiplies each element of VSR[VRA+32] by the corresponding element of VSR[VRC+32], adds the result to the corresponding element of VSR[VRB+32], and stores the final result in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    src3 ← VSR[VRC+32].word[i]
    result ← bfp32_MULTIPLY_ADD(src1,src3,src2)
    VSR[VRT+32].word[i] ← result
end

Programming Note

To use a multiply-add to perform an IEEE or Java compliant multiply, the addend must be -0.0.