lxv

Load VSX Vector

lxv XT, DQ(RA)

Loads a 128-bit vector from memory (VSX aligned offset).

Details

For lxv, the contents of the quadword in storage at address EA are placed into load_data. The order of bytes depends on the endianness (Big-Endian or Little-Endian). load_data is then placed into VSR[XT].

Pseudocode Operation

if 'lxv' & TX=0 & MSR.VSX=0 then VSX_Unavailable()
if 'lxv' & TX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA|0) + EXTS64(DQ||0b0000)
VSR[32×TX+T] ←MEM(EA,16)

Programming Note

The lxv instruction loads a 16-byte vector from memory into a VSX register. Ensure the address is properly aligned to avoid alignment faults. Check that the appropriate privilege levels (MSR.VSX for VSX operations and MSR.VEC for vector operations) are enabled before executing this instruction.

Example

lxv vs1, 0(r4)

Encoding

Binary Layout
0
0
T
6
RA
11
DQ
16
TX
28
1
31
 
Format DQ-form
Opcode 0xF4000001
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • DQ
    Offset
  • RA
    Base
  • disp
    Displacement value