divwu

Divide Word Unsigned

divwu RT, RA, RB

Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).

Details

The divwu instruction performs an unsigned division of a 64-bit dividend contained in two 32-bit registers by a 32-bit divisor. The quotient is placed into the upper 32 bits of the destination register, while the lower 32 bits are undefined. If the divisor is zero or if the quotient cannot be represented in 32 bits, the result is undefined.

Pseudocode Operation

RT <- (RA)[32:63] /u (RB)[32:63]

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divwu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
OE
21
459
22
Rc
31
 
Format XO-form
Opcode 0x7C000396
Extension Base
Registers Altered CR0

Operands

  • RT
    Target Register (Quotient)
  • RA
    Dividend
  • RB
    Divisor