divwu

Divide Word Unsigned

divwu RT, RA, RB

Divides the lower 32 bits of RA by the lower 32 bits of RB (Unsigned).

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

459

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000396

Extension Base

Operands

• RT
  Target Register (Quotient)
• RA
  Dividend
• RB
  Divisor

Example

divwu r3, r4, r5

// r3 = r4 / r5 (32-bit Unsigned).

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Divides the lower 32 bits of RA (treated as unsigned) by the lower 32 bits of RB (treated as unsigned) and places the 32-bit quotient in RT with the upper 32 bits of RT set to zero. If RB is zero, RT is undefined and no exception is raised (wrap-on-overflow behavior). When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.

Operation

dividend ← (RA)[32:63]
divisor ← (RB)[32:63]
if divisor = 0 then
  quotient ← undefined
else
  quotient ← dividend ÷ divisor
RT ← (0)32 || quotient
if Rc = 1 then
  CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.