xvmsubasp

VSX Vector Multiply-Subtract Type-A Single-Precision

xvmsubasp XT,XA,XB

Performs a vector multiply-subtract operation on single-precision floating-point values.

Encoding

Binary Layout

111100

0:5

XA

6:10

XT

11:15

XB

16:20

VX

21:28

000000

29

000000

30

000000

31

 

Format XX3-form

Opcode 0xF0000288

Extension VSX

Operands

• XT
  Destination Vector Register
• XA
  Source Vector Register A
• XB
  Source Vector Register B
• VX
  Target Vector Register

Example

xvmsubasp vs1, vs2, vs3

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a single-precision floating-point multiply-subtract operation (XT ← (XA × XB) - XT) on vector elements using the Type-A fused operation. This VSX instruction operates on two 128-bit vector registers, each containing four single-precision floating-point elements. The instruction does not affect condition registers or status flags; rounding behavior follows the FPSCR settings.

Operation

XT ← (XA × XB) - XT

Programming Note

The xvmsubasp instruction is commonly used for vectorized floating-point operations, particularly in scientific computing and graphics processing. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking the MSR.VSX bit; otherwise, a VSX_Unavailable exception will be raised. Be cautious of alignment requirements for vector registers to avoid performance penalties or exceptions. This instruction operates at user privilege level but can generate various floating-point exceptions based on the FPSCR settings, which should be handled appropriately in error-checking code.