mtvsrws

Move To VSR Word and Splat

mtvsrws XT, RA

Moves a 32-bit word from a GPR and replicates it across the vector.

Encoding

Binary Layout

31

0:5

XT

6:10

RA

11:15

0

16:20

243

21:31

 

Format XX1-form

Opcode 0x7C000326

Extension VSX

Operands

• XT
  Target
• RA
  Source GPR

Example

mtvsrws vs1, r4

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves the low 32 bits from GPR RA into a VSX register, then replicates that 32-bit word across all four 32-bit word positions in XT. This VSX instruction does not affect condition registers or status fields.

Operation

word ← RA[32:63]
for i in 0 to 3:
  XT[32*i:32*i+31] ← word

Programming Note

The mtvsrws instruction is used to move the upper 32 bits of a general-purpose register into the first word element of a vector-scalar register and splat it across the remaining elements. Ensure that the VSX or Vector facility is enabled in the MSR before using this instruction, otherwise, an exception will be raised. This instruction treats the operation as a Vector instruction, so developers should consider resource availability accordingly.