dcbtls

Data Cache Block Touch and Lock Set

dcbtls CT, RA, RB

Locks a cache line in the L1 cache.

Encoding

Binary Layout

31

0:5

CT

6:10

RA

11:15

RB

16:20

166

21:30

/

31

 

Format X-form

Opcode 0x7C00014C

Extension Privileged

Operands

• CT
  Cache Target
• RA
  Base
• RB
  Index

Example

dcbtls 0, r4, r5

Related

More in Privileged

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Locks a data cache line in the L1 data cache at the address computed from RA+RB. The cache target (CT) field specifies the cache level and operation type. This is a privileged instruction that provides cache locking hints to the processor and does not modify any general-purpose registers or condition flags.

Operation

EA ← (RA|0) + RB
Lock cache line at EA in L1 data cache based on CT