psth

Prefixed Store Halfword

psth RS, D(RA), R

Stores halfword using 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

44

32:37

RS

38:42

RA

43:47

D1

48:63

 

Format MLS:D-form

Opcode 0x06000000B0000000

Extension Prefixed

Operands

• RS
  Source
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

psth r3, 0(r4), 0

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores the least significant 16 bits of the source register to memory using a 34-bit signed offset (split between prefix and suffix). The effective address is computed from a base register or the program counter (determined by the R bit), supporting both absolute and PC-relative addressing modes. This is a two-instruction prefixed store with no condition register or status flag effects.

Operation

D ← EXTS(D0 || D1)
EA ← if R = 0 then (if RA = 0 then 0 else GPR[RA]) + D else CIA + D
MEM(EA, 2) ← GPR[RS][48:63]

Programming Note

The psth instruction is used to store the lower half of a doubleword from register RS into memory. It's important to ensure that RA and RB are correctly set to calculate the effective address. If RA is zero, the base address is considered as zero. This instruction operates at user privilege level and can raise an exception if there's a memory access violation.